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1/20 not for new design april 2001 this is information on a product still in production but not recommended for new designs. m28256 256 kbit (32k x 8) parallel eeprom with software data protection n fast access time: 90nsatv cc =5 v for m28256 120 ns at v cc =3 v for m28256-w n single supply voltage: 4.5 v to 5.5 v for m28256 2.7 v to 3.6 v for m28256-w n low power consumption n fast byte and page write (up to 64 bytes) 3 ms at v cc =4.5 v for m28256 5 ms at v cc =2.7 v for m28256-w n enhanced write detection and monitoring: data polling toggle bit page load timer status n jedec approved bytewide pin-out n software data protection n 100,000 erase/write cycles (minimum) n 10 year data retention (minimum) description the m28256 and m28256-w devices consist of 32k x 8 bits of low power, parallel eeprom, fab- ricated with stmicroelectronics' proprietary dou- ble polysilicon cmos technology. the devices offer fast access time, with low power dissipation, figure 1. logic diagram ai01885 15 a0-a14 w dq0-dq7 v cc m28256 g e v ss 8 table 1. signal names a0-a14 address input dq0-dq7 data input / output w write enable e chip enable g output enable v cc supply voltage v ss ground pdip28 (bs) so28 (ms) 300 mil width plcc32 (ka) 28 1 tsop28 (ns) 8 x 13.4 mm 28 1
m28256 2/20 figure 2a. dip connections figure 2b. pllc connections note: 1. nc = not connected 2. du = do not use a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 w a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 a14 v cc ai01886 m28256 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 ai01887 a13 a8 a10 dq4 17 a0 nc dq0 dq1 dq2 du dq3 a6 a3 a2 a1 a5 a4 9 w a9 1 a14 a11 dq6 a7 dq7 32 du v cc m28256 a12 nc dq5 g e 25 v ss figure 2c. so connections figure 2d. tsop connections dq0 dq1 a3 a0 a2 a1 a10 e a13 dq7 g dq5 v cc dq4 a9 w a4 a14 a7 ai01888 m28256 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 dq2 v ss a6 a5 dq6 28 27 26 25 24 23 a11 dq3 1 a12 a8 a1 a0 dq0 a5 a2 a4 a3 a9 a11 dq7 a8 g e dq5 dq1 dq2 dq3 dq4 dq6 a13 w a12 a6 a14 v cc a7 ai01889 m28256 28 1 22 78 14 15 21 v ss a10 and require a single voltage supply (5v or 3v, de- pending on the option chosen). the device has been designed to offer a flexible microcontroller interface, featuring both hardware and software handshaking, with ready/busy, data polling and toggle bit. the device supports a 64 byte page write operation. software data protection (sdp) is also supported, using the stan- dard jedec algorithm. signal description the external connections to the device are sum- marized in table 1, and their use in table 3. addresses (a0-a14). the address inputs are used to select one byte from the memory array during a read or write operation. data in/out (dq0-dq7). the contents of the data byte are written to, or read from, the memory array through the data i/o pins. chip enable (e). the chip enable input must be held low to enable read and write operations.
3/20 m28256 figure 3. block diagram ai01697 address latch a6-a14 (page address) x decode control logic 256k array address latch a0-a5 y decode v pp gen reset sense and data latch i/o buffers egw page load timer status toggle bit data polling dq0-dq7 table 2. absolute maximum ratings 1 note: 1. except for the rating aoperating temperature rangeo, stresses above those listed in the table aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality documents. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) symbol parameter value unit t a ambient operating temperature 40 to 85 c t stg storage temperature 65 to 150 c v cc supply voltage 0.3 to 6.5 v v io input or output voltage 0.3 to v cc +0.6 v v i input voltage 0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 2 4000 v
m28256 4/20 table 3. operating modes 1 note: 1. x = v ih or v il mode e g w dq0-dq7 read v il v il v ih data out write v il v ih v il data in stand-by / write-inhibit v ih x x hi-z write inhibit xx v ih data out or hi-z x v il x data out or hi-z output disable x v ih x hi-z when chip enable is high, power consumption is reduced. output enable (g). the output enable input con- trols the data output buffers, and is used to initiate read operations. write enable (w). the write enable input controls whether the addressed location is to be read, from or written to. device operation in order to prevent data corruption and inadvertent write operations, an internal v cc comparator in- hibits the write operations if the v cc voltage is lower than v wi (see table 4a and table 4b). once the voltage applied on the v cc pin goes over the v wi threshold (v cc >v wi ), write access to the memory is allowed after a time-out t puw , as spec- ified in table 4a and table 4b. further protection against data corruption is of- fered by the e and w low pass filters: any glitch, on the e and w inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory. read the device is accessed like a static ram. when e and g are low, and w is high, the contents of the addressed location are presented on the i/o pins. otherwise, when either g or e is high, the i/o pins revert to their high impedance state. write write operations are initiated when both w and e are low and g is high. the device supports both w-controlled and e-controlled write cycles (as shown in figure 10 and figure 11). the address is latched during the falling edge of w or e (which ever occurs later) and the data is latched on the rising edge of w or e (which ever occurs first). af- ter a delay, t wlq5h , that cannot be shorter than the value specified in table 9a and table 9b, the in- ternal write cycle starts. it continues, under inter- table 4a. power-up timing 1 for m28256 (5v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. sampled only, not 100% tested. table 4b. power-up timing 1 for m28256-w (3v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. sampled only, not 100% tested. symbol parameter min. max. unit t pur time delay to read operation 1 m s t puw time delay to write operation (once v cc v wi )5ms v wi write inhibit threshold 3.0 4.2 v symbol parameter min. max. unit t pur time delay to read operation 1 m s t puw time delay to write operation (once v cc v wi )10ms v wi write inhibit threshold 1.5 2.5 v
5/20 m28256 nal timing control, until the write operation is com- plete. the commencement of this period can be detected by reading the page load timer status on dq5. the end of the cycle can be detected by reading the status of the data polling and the tog- gle bit functions on dq7 and dq6. page write the page write mode allows up to 64 bytes to be written on a single page in a single go. this is achieved through a series of successive write op- erations, no two of which are separated by more than the t wlq5h value (as specified in table 9a and table 9b). the page write can be initiated during any byte write operation. following the first byte write in- struction the host may send another address and data with a minimum data transfer rate of: 1/t wlq5h . the internal write cycle can start at any instant af- ter t wlq5h . once initiated, the write operation is in- ternally timed, and continues, uninterrupted, until completion. all bytes must be located on the same page ad- dress (a14-a6 must be the same for all bytes). otherwise, the page write operation is not execut- ed. as with the single byte write operation, described above, the dq5, dq6 and dq7 lines can be used to detect the beginning and end of the internally controlled phase of the page write cycle. software data protection (sdp) the device offers a software-controlled write-pro- tection mechanism that allows the user to inhibit all write operations to the device. this can be useful for protecting the memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). by default, the device is shipped in the aunprotect- edo state: the memory contents can be freely changed by the user. once the software data pro- tection mode is enabled, all write commands are ignored, and have no effect on the memory con- tents. the device remains in this mode until a valid soft- ware data protection disable sequence is re- ceived. the device reverts to its aunprotectedo state. the status of the software data protection (en- abled or disabled) is represented by a non-volatile latch, and is remembered across periods of the power being off. the software data protection enable command consists of the writing of three specific data bytes figure 4. software data protection enable algorithm and memory write note: 1. the most significant address bits (a14 to a6) differ during these specific page write operations. ai01698c write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h sdp is set write aah in address 5555h write 55h in address 2aaah write a0h in address 5555h write data to be written in any address sdp enable algorithm page write timing page write timing write is enabled sdp set sdp not set write in memory write data + sdp set after twc
m28256 6/20 to three specific memory locations (each location being on a different page), as shown in figure 4. similarly to disable the software data protection, the user has to write specific data bytes into six dif- ferent locations, as shown in figure 5. this com- plex series of operations protects against the chance of inadvertent enabling or disabling of the software data protection mechanism. when sdp is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inad- vertent use). the sequence is as shown in figure 4. this consists of an unlock key, to enable the write action, at the end of which the sdp continues to be enabled. this allows the sdp to be enabled, and data to be written, within a single write cycle (t wc ). status bits the devices provide three status bits (dq7, dq6 and dq5), and one output pin (rb), for use during write operations. these allow the application to use the write time latency of the device for getting on with other work. these signals are available on the i/o port bits dq7, dq6 and dq5 (but only dur- ing programming cycle, once a byte or more has been latched into the memory) or continuously on the rb output pin. data polling bit (dq7). the internally timed write cycle starts after t wlq5h (defined in table 9a and table 9b) has elapsed since the previous byte was latched in to the memory. the value of the dq7 bit of this last byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is in- verted back to its original value once the operation is complete. toggle bit (dq6). the device offers another way for determining when the internal write cycle is completed. during the internal erase/write cycle, dq6 toggles from '0' to '1' and '1' to '0' (the first read value being '0') on subsequent attempts to read any byte of the memory. when the internal figure 5. software data protection disable algorithm ai01699c write aah in address 5555h write 55h in address 2aaah write 80h in address 5555h unprotected state after twc (write cycle time) write aah in address 5555h write 55h in address 2aaah write 20h in address 5555h page write timing figure 6. status bit assignment ai02855 dp tb plts x xxxx dp tb plts x dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 = data polling = toggle bit = page load timer status = don't care
7/20 m28256 write cycle is complete, the toggling is stopped, and the values read on dq7-dq0 are those of the addressed memory byte. this indicates that the device is again available for new read and write operations. page load timer status bit (dq5). an internal timer is used to measure the period between suc- cessive write operations, up to t wlq5h (defined in table 9a and table 9b). the dq5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). the dq5 line is held high when the counter has overflowed (hence showing that the device is now starting the internal write to the memory array). table 5a. read mode dc characteristics for m28256 (5v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. all inputs and outputs open circuit. table 5b. read mode dc characteristics for m28256-w (3v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. all inputs and outputs open circuit. symbol parameter test condi tion min. max. unit i li input leakage current 0 v v in v cc 10 m a i lo output leakage current 0 v v out v cc 10 m a i cc 1 supply current (ttl inputs) e=v il ,g=v il , f = 5 mhz 30 ma supply current (cmos inputs) e=v il ,g=v il , f = 5 mhz 25 ma i cc1 1 supply current (stand-by) ttl e=v ih 1ma i cc2 1 supply current (stand-by) cmos e>v cc 0.3v 100 m a v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = 400 m a 2.4 v symbol parameter test condi tion min. max. unit i li input leakage current 0 v v in v cc 10 m a i lo output leakage current 0 v v out v cc 10 m a i cc 1 supply current (cmos inputs) e=v il ,g=v il , f = 5 mhz, v cc = 3.3v 15 ma e=v il ,g=v il , f = 5 mhz, v cc = 3.6v 15 ma i cc2 1 supply current (stand-by) cmos e>v cc 0.3v 20 m a v il input low voltage 0.3 0.6 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 1.6 ma 0.2 v cc v v oh output high voltage i oh = 400 m a 0.8 v cc v
m28256 8/20 table 6. input and output parameters 1 (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. table 7. ac measurement conditions symbol parameter test condition min. max. unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf input rise and fall times 20 ns input pulse voltages (m28256) 0.4 v to 2.4 v input pulse voltages (m28256-w) 0 v to v cc 0.3v input and output timing reference voltages (m28256) 0.8 v to 2.0 v input and output timing reference voltages (m28256-w) 0.5 v cc figure 7. ac testing input output waveforms ai02101b 4.5v to 5.5v operating voltage 2.7v to 3.6v operating voltage v cc 0.3v 0v 0.5 v cc 2.4v 0.4v 2.0v 0.8v figure 8. ac testing equivalent load circuit ai02102b out c l = 100pf c l includes jig capacitance i ol device under test i oh table 8a. read mode ac characteristics for m28256 (5v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. output hi-z is defined as the point at which data is no longer driven. symbol alt. parameter test conditi on m28256 unit -90 -12 -15 -20 min max min max min max min max t avqv t acc address valid to output valid e=v il , g=v il 90 120 150 200 ns t elqv t ce chip enable low to output valid g=v il 90 120 150 200 ns t glqv t oe output enable low to output valid e=v il 40 45 50 50 ns t ehqz 1 t df chip enable high to output hi-z g=v il 0 40 0 45 0 50 0 50 ns t ghqz 1 t df output enable high to output hi-z e=v il 0 40 0 45 0 50 0 50 ns t axqx t oh address transition to output transition e=v il , g=v il 0000ns
9/20 m28256 table 8b. read mode ac characteristics for m28256-w (3v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. output hi-z is defined as the point at which data is no longer driven. symbol alt. parameter test conditi on m28256-w unit -12 -15 -20 -25 min max min max min max min max t avqv t acc address valid to output valid e=v il , g=v il 120 150 200 250 ns t elqv t ce chip enable low to output valid g=v il 120 150 200 250 ns t glqv t oe output enable low to output valid e = v il 45 70 80 100 ns t ehqz 1 t df chip enable high to output hi-z g = v il 0 45 0 50 0 55 0 60 ns t ghqz 1 t df output enable high to output hi-z e=v il 0 45 0 50 0 55 0 60 ns t axqx t oh address transition to output transition e=v il , g=v il 0000ns figure 9. read mode ac waveforms (with write enable, w, high) note: 1. write enable (w) = v ih ai01700 valid tavqv taxqx tglqv tehqz tghqz data out a0-a14 e g dq0-dq7 telqv hi-z
m28256 10/20 table 9a. write mode ac characteristics for m28256 (5v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 4.5 to 5.5 v) note: 1. characterized only; not tested in production. symbol alt. parameter test condit ion m28256 unit min max t avwl t as address valid to write enable low e=v il ,g=v ih 0ns t avel t as address valid to chip enable low g=v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g=v ih 0ns t ghwl t oes output enable high to write enable low e = v il 0ns t ghel t oes output enable high to chip enable low w=v il 0ns t wlel t wes write enable low to chip enable low g = v ih 0ns t wlax t ah write enable low to address transition 50 ns t elax t ah chip enable low to address transition 50 ns t wldv t dv write enable low to input valid e=v il ,g=v ih 1 m s t eldv t dv chip enable low to input valid g=v ih ,w=v il 1 m s t eleh t wp chip enable low to chip enable high 50 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0 ns t ehgl t oeh chip enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 50 1000 ns t wlwh t wp write enable low to write enable high 50 ns t wlq5h t blc time-out after last byte write 150 m s t q5hq5x t wc write cycle time 5 ms t wl write enable input filter pulse width note 1 10 ns t el chip enable input filter pulse width note 1 10 ns t dvwh t ds data valid before write enable high 50 ns t dveh t ds data valid before chip enable high 50 ns
11/20 m28256 table 9b. write mode ac characteristics for m28256-w (3v range) (t a = 0 to 70 c or -40 to 85 c; v cc = 2.7 to 3.6 v) note: 1. characterized only; not tested in production. symbol alt. parameter test condit ion m28256-w unit min max t avwl t as address valid to write enable low e=v il ,g=v ih 0ns t avel t as address valid to chip enable low g=v ih ,w=v il 0ns t elwl t ces chip enable low to write enable low g=v ih 0ns t ghwl t oes output enable high to write enable low e = v il 0ns t ghel t oes output enable high to chip enable low w=v il 0ns t wlel t wes write enable low to chip enable low g = v ih 0ns t wlax t ah write enable low to address transition 70 ns t elax t ah chip enable low to address transition 70 ns t wldv t dv write enable low to input valid e=v il ,g=v ih 1 m s t eldv t dv chip enable low to input valid g=v ih ,w=v il 1 m s t eleh t wp chip enable low to chip enable high 100 1000 ns t wheh t ceh write enable high to chip enable high 0 ns t whgl t oeh write enable high to output enable low 0 ns t ehgl t oeh chip enable high to output enable low 0 ns t ehwh t weh chip enable high to write enable high 0 ns t whdx t dh write enable high to input transition 0 ns t ehdx t dh chip enable high to input transition 0 ns t whwl t wph write enable high to write enable low 100 1000 ns t wlwh t wp write enable low to write enable high 100 ns t wlq5h t blc time-out after the last byte write 200 m s t q5hq5x t wc write cycle time 5 ms t wl write enable input filter pulse width note 1 10 ns t el chip enable input filter pulse width note 1 10 ns t dvwh t ds data valid before write enable high 50 ns t dveh t ds data valid before chip enable high 50 ns
m28256 12/20 figure 10. write mode ac waveforms (write enable, w, controlled) figure 11. write mode ac waveforms (chip enable, e, controlled) ai01701 valid tavwl a0-a14 e g dq0-dq7 data in w twlax telwl tghwl twldv twheh twhgl twlwh twhwl twhdx tdvwh ai01702 valid tavel a0-a14 e g dq0-dq7 data in w telax tghel twlel teldv tehgl tehdx tdveh teleh tehwh
13/20 m28256 figure 12. page write mode ac waveforms (write enable, w, controlled) figure 13. software protected write cycle waveforms note: 1. a14 to a6 must specify the same page address during each high-to-low transition of w (or e). g must be high only when w and e are both low. ai01703b a0-a14 e g dq0-dq7 w twhwh addr 0 dq5 addr 1 addr 2 addr n twhwh twhrh twlwh twhwl byte 0 byte 1 byte 2 byte n byte n ai01704 a0-a5 e g dq0-dq7 w twlwh tdvwh byte 0 twhwl a6-a14 twlax twhwh twhdx tavel 5555h 2aaah 5555h byte 62 byte 63 aah 55h a0h byte address page address
m28256 14/20 figure 14. data polling sequence waveforms figure 15. toggle bit sequence waveforms note: 1. the toggle bit is first set to `0'. ai01705 a0-a14 e g dq7 w dq7 dq7 dq7 dq7 dq7 ready last write internal write sequence address of the last byte of the page write instruction ai01706 a0-a14 e g dq6 w ready last write internal write sequence (1) toggle dq6 dq6
15/20 m28256 table 10. ordering information scheme note: 1. available for the 3v range (m28256-w) only. 2. available for the 5v range (m28256) only. 3. temperature range on request only. example: m28256 15 w ka 6 t speed option 90 1 90 ns t tape and reel packing 12 120 ns 15 150 ns temperature range 20 200 ns 1 3 0 cto70 c 25 2 250 ns 6 40 cto85 c operating voltage package blank 4.5 v to 5.5 v bs pdip28 w 2.7 v to 3.6 v ka plcc32 ms so28 (300 mil width) ns tsop28 (8 x 13.4 mm) ordering information devices are shipped from the factory with the memory content set at all `1's (ffh). the notation used for the device number is as shown in table 10. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you.
m28256 16/20 figure 16. pdip28 (bs) note: 1. drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2 table 11. pdip28 - 28 pin plastic dip, 600 mils width symb. mm inches typ. min. max. typ. min. max. a 3.94 5.08 0.155 0.200 a1 0.38 1.78 0.015 0.070 a2 3.56 4.06 0.140 0.160 b 0.38 0.56 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.30 0.008 0.012 d 34.70 37.34 1.366 1.470 e 14.80 16.26 0.583 0.640 e1 12.50 13.97 0.492 0.550 e1 2.54 0.100 ea 15.20 17.78 0.598 0.700 l 3.05 3.82 0.120 0.150 s 1.02 2.29 0.040 0.090 a 0 15 0 15 n28 28
17/20 m28256 table 12. plcc32 - 32 lead plastic leaded chip carrier, rectangular symbol mm inches typ. min. max. typ. min. max. a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 0.050 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 figure 17. plcc (ka) note: 1. drawing is not to scale. plcc d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2
m28256 18/20 table 13. so28 - 28 lead plastic small outline, 300 mils body width symb. mm inches typ. min. max. typ. min. max. a 2.46 2.64 0.097 0.104 a1 0.13 0.29 0.005 0.011 a2 2.29 2.39 0.090 0.094 b 0.35 0.48 0.014 0.019 c 0.23 0.32 0.009 0.013 d 17.81 18.06 0.701 0.711 e 7.42 7.59 0.292 0.299 e 1.27 0.050 h 10.16 10.41 0.400 0.410 l 0.61 1.02 0.024 0.040 a 0 8 0 8 n28 28 cp 0.10 0.004 figure 18. so28 wide (ms) note: 1. drawing is not to scale. so-b e n cp b e a2 d c l a1 a h a 1
19/20 m28256 table 14. tsop28 - 28 lead plastic thin small outline, 8 x 13.4 mm symb. mm inches typ. min. max. typ. min. max. a 1.25 0.049 a1 0.20 0.008 a2 0.95 1.15 0.037 0.045 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 13.20 13.60 0.520 0.535 d1 11.70 11.90 0.461 0.469 e 7.90 8.10 0.311 0.319 e 0.55 0.022 l 0.50 0.70 0.020 0.028 a 0 5 0 5 n28 28 cp 0.10 0.004 figure 19. tsop28 (ns) note: 1. drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
m28256 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. ? 2001 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http:// www.st.com

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